As is known, remarkable progress has been made in the manufacture of Dynamic Random Access Memories (DRAM) using high integration technology. For example, main stream production has changed from 64K bits to 256K bits, and the manufacture of from 1Mbit DRAMs to 64M bit DRAMs has been achieved.
In such a DRAM with high integration, a predetermined capacitance of the cell storage capacitor must be kept constant, despite the decrease in the area of the cells. For example, the area of a cell in a 64M bit DRAM decreases to about 1.4 .mu.m.sup.2.
In the case where the areas of charge storage capacitors are also decreased and the capacitance becomes small, a so-called soft error occurs on exposure to .alpha.-light, and the problem of reliability on a semiconductor device becomes an issue. Therefore, in order to obtain an improved integration of a semiconductor device, the capacitance of cell storage capacitors must be kept constant, despite the decrease in the areas of the capacitors.
In a recent DRAM whose storage cells are based on transistor-stacked capacitor combinations, one of a pair of electrodes of a storage capacitor has been formed to have a three-dimensional structure. This makes the capacitance larger by 30 to 40% than that of a two-dimensional storage capacitor having the same size as the three-dimensional one. In the case of 64M bit DRAMs having high integration, the capacitance needs to increase without the increase of cell areas or storage area, and various three-dimensional structures or high dielectric constant have been studied.
One method for obtaining a high capacitance in defined small areas of capacitors, such as the above three-dimensional DRAMs, is described in "Solid State Device & Material No. 90-167", page 49, published December, 1990. A method for manufacturing the same will be described in the light of the accompanying drawings.